In many electronic control systems, it is desirable to produce digital pulse-width modulation (DPWM) signals with high resolution—that is, to allow small adjustments in the pulse width. One common method of generating a DPWM signal is to use a traditional digital counter followed by a comparator. In such a system, a clock with a known frequency runs a counter, and the output of the counter is fed into a comparator that compares the clock count to the digital PWM command. The output of the comparator is high at the beginning of each cycle and is reset when the two codes match. This approach is limited in that it requires a very high frequency clock to achieve high resolution DPWM signals.
Another conventional method of generating a DPWM signal is to pass a clock signal through an 2N-stage delay-locked loop (DLL) with the DLL locked so that a single stage delay is equal to the required resolution. Each stage of the DLL is selectable via a 2N:1 multiplexer (or “MUX”) with an N-bit DPWM command word tied to the MUX select. The difference between the input of the DLL and the output of the MUX will be the desired DPWM signal. With this approach, the clock frequency can be fixed to a relatively low value; however, a large number of delay stages will be needed for fine resolution, resulting in high power dissipation. In addition, the highest achievable resolution is limited by the fabrication method itself.
In other conventional systems, a medium-frequency clock is used to run both a counter and a DLL. The counter is used to resolve the m most significant bits (MSBs), while the remaining n=N−m least significant bits (LSBs) are resolved by the DLL. This approach combines the hardware efficiency of the counter-based method with the low frequency clock of the DLL method. However, the maximum resolution is still limited by the minimum designable delay for a given process. Also, to achieve n bits of LSB resolution, 2n delay stages are required.
Another conventional method uses a two-stage approach, where the first stage is a DLL that resolves the MSBs, and the second stage takes in two consecutive tap-points of the DLL and uses a secondary DLL to ensure that the delay cell has the desired resolution. It is a monotonic (always increasing) DPWM, but is generally not practical for fine resolutions because it relies on very small changes in capacitance to generate the fine delay.
Accordingly, it would be desirable to provide DPWM circuits with improved resolution. Other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.